High-Conversion-Ratio Bidirectional DC–DC Converter With Dual Coupled Inductors

In this paper, a high-conversion-ratio bidirectional DC–DC converter with dual coupled inductors is proposed. In the boost mode, two capacitors are parallel charged and series discharged by the dual coupled inductors. Thus, high step-up voltage gain can be achieved with an appropriate duty ratio. In the buck mode, two capacitors are series charged and parallel discharged by the dual coupled inductors. The bidirectional converter can have high step-down voltage gain. The stress voltage of all switches can be reduced, and the switching loss and efficiency can be improved. The operating principle and the steady-state analyses of the voltage gain are discussed. Finally, in 24V for low voltage, and 400V for high voltage, and 200W for output power, this converter simulated in MATLAB

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether natural or stemming from soft errors, can result in gate malfunction, ultimately leading to erroneous multiplier outputs. Thus, to prevent susceptibility to error, it is imperative to employ an effective finite field multiplier implementation that boasts a robust fault detection capability. This study proposes a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), intended to achieve optimal fault detection performance for finite field multipliers while simultaneously maintaining a low-complexity implementation, a favored attribute in resource-constrained applications like smart cards. The primary concept behind the proposed approach is centered on the implementation of a BCH decoder that utilizes re-encoding technique and FIBM algorithm in its first and second sub-modules, respectively. This approach serves to address hardware complexity concerns while also making use of Berlekamp-Rumsey-Solomon (BRS) algorithm and Chien search method in the third sub-module of the decoder to effectively locate errors with minimal delay. The results of our synthesis indicate that our proposed error detection and correction architecture for a 45-bit multiplier with 5-bit errors achieves a 37% and 49% reduction in critical path delay compared to existing designs. Furthermore, the hardware complexity associated with a 45-bit multiplicand that contains 5 errors is confined to a mere 80%, which is significantly lower than the most exceptional BCH-based fault recognition methodologies, including TMR, Hamming's single error correction, and LDPC-based procedures within the realm of finite field multiplication.Comment: 9 pages, 4 figures. arXiv admin note: substantial text overlap with arXiv:2209.1338

Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

Finite field multiplier is mainly used in elliptic curve cryptography, error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field GF(2m) which requires a huge amount of logic resources. In this paper, a new modified serial-in parallel-out multiplication algorithm with interleaved modular reduction is suggested. The proposed method offers efficient area architecture as compared to proposed algorithms in the literature. The reduced finite field multiplier complexity is achieved by means of utilizing logic NAND gate in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity. A detailed comparative analysis indicates that, the proposed finite field multiplier based on logic NAND gate outperforms previously known resultsComment: 19 pages, 4 figure

A Highly Efficient and Linear Class AB Power Amplifier for RFID Application

Power amplifiers (PAs) are usually the largest consumer of power in the transmitter. Therefore, designing a high efficiency RF power amplifier might be the best solution to cope with the problem of battery lifetime limitations in portable RFID code reader. In this paper, the designed circuit in Agilent ADS software is implemented using 0.18 μm RFCMOS technology at 3.3 v supply voltage. The measured results indicate that power added efficiency,out put power and power gain of the proposed class AB power amplifier at frequency of 2.4GHz are 35% , 30dBm and 28dBm

Design of a Class F Power Amplifier With 60% Efficiency at 1800 MHz Frequency

Based on the portable systems application, it is necessary to design blocks with high efficiency to increase battery lifetime. Power amplifier is the highest power consumption block in transmitter. The proposed circuit was simulated using ADS Agilent based on 0.18 μm TSMC RF CMOS technology and supply voltage of 3.3V on transistor level. The proposed power amplifier was designed by Class F type at 1800 MHz with 60% efficiency and output powers of 30 dBm

Evaluation and ranking of factors affecting the effectiveness of online education through TOPSIS (case study: specialized webinars of educational groups in North Khorasan education)

Background and Aim: This research aims to evaluate the effectiveness of online courses in specialized webinars of educational groups in North Khorasan education. Methods: This research was conducted using a survey method, and the statistical population of this research is 180 online course teachers. A statistical sample of 118 people was selected based on the table of Krejecie and Morgan. The data collection tool is a researcher-made questionnaire. Data analysis was done on two levels (descriptive and inferential statistics (one-sample t-test). Results: The results of the research showed that content elements, page design, organization of educational materials, flexibility, workload, and evaluation methods affect the effectiveness of online education. It significantly affects the specialized webinars of educational groups in the education and training of North Khorasan. In addition, the elements of teaching-learning activities, providing feedback, helping the participants and the ability to motivate the participants are insignificant. These elements are at an average level of effectiveness. Conclusion:  Prioritization with TOPSIS showed that educational content, organization of educational materials, assistance, flexibility, motivation, appropriate volume, evaluation methods, teaching-learning activities, appropriate design of pages, and feedback are influential factors for online education

Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code

The finite field multiplier is mainly used in many of today's state of the art digital systems and its hardware implementation for bit parallel operation may require millions of logic gates. Natural causes or soft errors in digital design could cause some of these gates to malfunction in the field, which could cause the multiplier to produce incorrect outputs. To ensure that they are not susceptible to error, it is crucial to use a finite field multiplier implementation that is effective and has a high fault detection capability. In this paper, we propose a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), where the proposed method aims at obtaining high fault detection performance for finite field multipliers and meanwhile maintain low-complexity implementation which is favored in resource constrained applications such as smart cards. The proposed method is based on BCH error correction codes, with an area-delay efficient architecture. The experimental results show that for 45-bit multiplier with 5-bit errors the proposed error detection and correction architecture results in 37% and %49 reduction in critical path delay with compared to the existing method in [18]. Moreover, the area overhead for 45-bit multiplier with 5 errors is within 80% which is significantly lower than the best existing BCH based fault detection method in finite field multiplier [18].Comment: There are some errors in simulation result

Circuit and system design for an 860-960?MHz RFID reader front-ends with Tx leakage suppression in 0.18-mu m CMOS technology

This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-mu m technology. The chip area is 2.65?mm x 1.35?mm including the bonding pads. The PA delivers an output power of 29?dBm and a power-added efficiency of 24% with a power gain of 20?dB, including the losses of the bond-wires. Copyright (C) 2011 John Wiley & Sons, Ltd